Design And Reuse

Andes Technology Launches RISC-V Now! — A Global Conference Series Focused on Commercial, Production-Scale RISC-V

RISC-V Now! evolves Andes’ long-running RISC-V CON events, which last year attracted more than 1,100 registrations and 550 in-person attendees globally, with a senior audience dominated by engineering ...
New Electronics

CAST looks to simplify RISC-V IP adoption with new program

This program is a new way for embedded system developers to adopt RISC-V processors faster and with less risk. Catalyst combines CAST’s 32-bit RISC-V processor IP cores with simplified configurations, ...

Bolt wants to take on Nvidia by building a RISC-V graphics processor

Bolt Graphics wants to take on Nvidia and AMD by building a RISC-V graphics processor ...
WREG

CEVA Joins Intel Pathfinder for RISC-V Program

CEVA-BX1 and CEVA-BX2 Audio DSPs and audio front-end software to be available through Intel Pathfinder for RISC-V ROCKVILLE, Md., Dec. 1, 2022 /PRNewswire/ -- CEVA, Inc. (NASDAQ: CEVA), the leading ...
Design-Reuse

CAST Simplifies RISC-V Embedded Processor IP Adoption with New Catalyst Program

Targeted, preconfigured RISC-V IP cores plus low-risk, easy-start, deferred-payment IP licensing make embedded RISC-V design easier than ever Santa Clara, California, RISC-V Summit — October 22, 2025 ...
Nasdaq

Microchip Unveils Family Details and Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC FPGA Family

BANGKOK, Dec. 12, 2019 /PRNewswire/ -- RISC-V Summit -- The trend towards compute intensive gateways and edge devices is driving the integration of traditional deterministic control applications with ...

WebAssembly: Wasmer 7.0 brings experimental async support for Python

The runtime offers new features for Python: an experimental async API and access to many native Python libraries like NumPy.
CNX Software

FOSDEM 2026 schedule – Embedded, RISC-V, Robotics, Rust, Open Hardware, and more

FOSDEM 2026 will take place on January 31-February 1, with thousands of developers meeting in Brussels to discuss open-source ...
Semiconductor Engineering

FPGA-Proven RISC-V System With Hardware Accelerated Task Scheduling

A technical paper titled “Enabling HW-based Task Scheduling in Large Multicore Architectures” was published by researchers at Barcelona Supercomputing Center, University of Campinas, University of Sao ...
Ars Technica

16-bit RISC-V processor made with carbon nanotubes

Our ability to continuously shrink the features of our silicon-based processors appears to be a thing of the past, which has materials scientists considering ways to move beyond silicon. The top ...
Semiconductor Engineering

RISC-V Wants All Your Cores

RISC-V is no longer content to disrupt the CPU industry. It is waging war against every type of processor integrated into an SoC or advanced package, an ambitious plan that will face stiff competition ...
9to5Mac

Apple exploring open-source RISC-V chips, but almost certainly not instead of ARM

An Apple job ad reveals that the company is exploring the use of RISC-V chips, an open-source processor tech that competes with the ARM architecture used for Apple’s A-series and M-series chips.