Santa Cruz, Calif. — Working to support modeling and verification at a higher level of abstraction, Jeda Technologies is adding transaction-level assertion to native SystemC assertion (NSCa), a ...
Santa Cruz, Calif. — A transaction-level modeling standard for silicon intellectual property will roll out this week that promises to bring chip designers above the register-transfer level. The Open ...
SLD: How long has NXP designed at the system-level for production chips? Frans Theeuwen: It depends on what you call ‘system-level design.’ We have been doing hardware/software co-verification ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results